1. Field of the Invention
The present invention relates generally to electronic comparators and more particularly to latched comparators.
2. Description of the Related Art
FIG. 1 shows a latched comparator 20 that illustrates conventional concepts in the comparator art (e.g., it is similar to comparator AM685 that is available from Advanced Micro Devices, Inc., 901 Thompson Place, Sunnyvale, Calif.). It includes an input differential pair 22 of transistors 24 and 25 whose bases form an input signal port 28. The comparator also has an emitter-follower output buffer 30 of transistors 32 and 33 whose emitters are connected by zener diodes 36 to first and second output signal paths 37 and 38 that form an output signal port 39. Collectors of the emitter-follower output buffer 30 are connected to a supply source V.sub.CC and resistors 40 couple bases of the emitter-follower buffer 30 to the supply source V.sub.CC.
A common-base output stage 42 of transistors 43 and 44 is coupled between the input differential pair 22 and the emitter-follower output buffer 30. Bases of the common-base output stage 42 are biased through a bias port 45 and a clamp 46 formed of oppositely-directed Schottky diodes 48 connects the bases of the emitter-follower output buffer 30.
A latch 50 is formed with a first latch differential pair 52 of transistors 53 and a second latch differential pair 54 of transistors 55. The first differential pair 52 has each of its bases connected to a respective one of the output signal paths 37 and 38 and each of its collectors connected to a respective one of collectors of the input differential pair 22. These bases and collectors are cross-coupled relative to each other, i.e., each of the transistors 53 has its base connected to one of the first and second output signal paths 37 and 38 and its collector connected to a side of the common-base output stage 42 that leads to the other of the first and second output signal paths 37 and 38.
The second latch differential pair 54 has one of its collectors supplying current to the first differential pair 52 (i.e., to the coupled emitters of this differential pair) and the other of its collectors is connected to the supply source V.sub.CC. Bases of the differential pair 54 form a latch signal port 56.
Essentially, each transistor of the first latch differential pair 52 holds the current state of a respective transistor of the input differential pair 22 during the presence of a latch signal.
The zener diodes 36, the emitters of the second latch differential pair 54 and the emitters of the input differential pair 22 are respectively biased on via current sources 60, 62, 64 and 66.
In many comparator applications, a signal at one signal path of the input port 28 is compared to a threshold voltage V.sub.thld that is applied at the other input signal path as indicated in broken lines in FIG. 1. In absence of the latch 50, an output signal at the comparator's output port 39 will then indicate the relationship between the input signal and the threshold voltage V.sub.thld. When a latch signal is applied to the latch port 56, the output signal at port 39 represents the relationship between the input signal and the threshold voltage V.sub.thld at times specified by the latch signal. In this mode, the comparator is often referred to as a sampler because it "samples" the input signal at times defined by the latch signal.
Although suitable for general operation, several structural portions of the comparator 20 limit its application at higher speeds. To enhance high-speed operation, it is critical that a comparator's propagation delay be substantially insensitive to input signal conditions (e.g., rise time, slew rate, overdrive, signal polarity, duty cycle and common-mode signals). In contrast, propagation delays in the comparator 20 are sensitive to all of these parameters.
Because of the comparator's structure, for example, differential heating in the input differential pair 22 is a function of signal duty cycle and this heating will affect signal propagation delay. If the base of transistor 24 is above that of transistor 25, transistor 24 carries a greater current and dissipates a greater power. The resultant unequal heating in the input differential pair 22 induces a differential change in base-emitter voltage (on the order of 2 mV/degree Centigrade) which acts as a time-dependent input-signal offset that converts into a propagation delay change.
This susceptibility to thermal heating is also caused, in part, because the common-base output stage 42 must be biased (via the bias port 45) close to V.sub.CC to accommodate the positive portion of the input's common-mode signal range. Accordingly, the input differential pair 22 has large collector-to-emitter voltages and large power differentials. In addition, the collector-to-emitter voltages of transistors 24 and 25 are a function of common mode which induces further differential heating and consequent changes in propagation delay. Propagation delays in the comparator 20, therefore, have an undesirable sensitivity to common-mode signals.
Propagation delays are also sensitive to input signal swing and signal rise time. A parasitic capacitance (due to comparator structures such a signal traces) will exist at the emitters of the input differential pair 22. In the comparator 20, the input differential pair must track the full extent of the input-signal range and, accordingly, propagation delays caused by charging of the parasitic capacitance will be greater for a small, slow input signal swing than for a fast, large signal change. For a small, slow change, the parasitic capacitance represents a light load to the input differential pair 22. In contrast, it represents a large load for fast, large changes. Because the input differential pair 22 tracks the entire input-signal range, its sensitivity to signal swing and rise time is therefore increased.
The comparator 20 is also limited in its input differential-signal range and in its bandwidth. The first limitation results because the input signal range cannot exceed the base-to-emitter breakdown voltage of the transistors 24 and 25 which is typically on the order of a couple of volts. The second limitation results because the comparator 20 requires the Schottky diodes 48 to limit signal swings at the collectors of transistors 43 and 44 so as to prevent their saturation. However, these diodes compromise the comparator's bandwidth.